PCI2050 datasheet(32/81 Pages) TI

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µs and 993 µs, respectively). PCI Local Bus Specification recommends that a bridge wait 215 PCI clocks before

discarding the transaction data or status.

The PCI2050 implements a discard timer for use in delayed transactions. After a delayed transaction is completed

on the destination bus, the bridge may discard it under two conditions. The first condition occurs when a read

transaction is made to a region of memory that is inside a defined prefetchable memory region, or when the command

is a memory read line or a memory read multiple, implying that the memory region is prefetchable. The other condition

occurs when the master originating the transaction (either a read or a write, prefetchable or nonprefetchable) has not

retried the transaction within 210 or 215 clocks. The number of clocks is tracked by a timer referred to as the discard

timer. When the discard timer expires, the bridge is required to discard the data. The PCI2050 default value for the

discard timer is 215 clocks; however, this value can be set to 210 clocks by setting bit 9 in the bridge control register

(offset 3Eh, see Section 4.32). For more information on the discard timer, see

error conditions in PCI Local Bus

Specification.

3.12 Delayed Transactions

The bridge supports delayed transactions as defined in

PCI Local Bus Specification. A target must be able to complete

the initial data phase in 16 PCI clocks or less from the assertion of the cycle frame (FRAME), and subsequent data

phases must complete in eight PCI clocks or less. A delayed transaction consists of three phases:

•

An initiator device issues a request.

•

The target completes the request on the destination bus and signals the completion to the initiator.

•

The initiator completes the request on the originating bus.

If the bridge is the target of a PCI transaction and it must access a slow device to write or read the requested data,

and the transaction takes longer than 16 clocks, then the bridge must latch the address, the command, and the byte

enables, and then issue a retry to the initiator. The initiator must end the transaction without any transfer of data and

is required to retry the transaction later using the same address, command, and byte enables. This is the first phase

of the delayed transaction.

During the second phase, if the transaction is a read cycle, the bridge fetches the requested data on the destination

bus, stores it internally, and obtains the completion status, thus completing the transaction on the destination bus.

If it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the

transaction on the destination bus. The bridge stores the completion status until the master on the initiating bus retries

the initial request.

During the third phase, the initiator rearbitrates for the bus. When the bridge sees the initiator retry the transaction,

it compares the second request to the first request. If the address, command, and byte enables match the values

latched in the first request, then the completion status (and data if the request was a read) is transferred to the initiator.

At this point, the delayed transaction is complete. If the second request from the initiator does not match the first

request exactly, then the bridge issues another retry to the initiator.

The PCI supports up to three delayed transactions in each direction at any given time.

3.13 Mode Selection

Table 3–3 shows the mode selection via MS0 (PDV terminal 155, GHK terminal E17) and MS1 (PDV terminal 106,

GHK terminal R17).

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