PCI2050 datasheet(66/81 Pages) TI

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5–10

5.13 Power Management Control/Status Register

The power management control/status register determines and changes the current power state of the PCI2050. The

contents of this register are not affected by the internally generated reset caused by the transition from D3hot to D0

state.

Bit

Name

Power management control/status

Type

R/W

Default

Power management control/status

Type:

Read-only, Read/Write

Offset:

E0h

Default:

0000h

Table 5–11. Power Management Control/Status Register

BIT

TYPE

FUNCTION

PME status. This bit returns a 0 when read because the PCI2050 does not support PME.

14–13

Data scale. This two-bit read-only field indicates the scaling factor to be used when interpreting the value of the

data register. These bits return only 00b, because the data register is not implemented.

12–9

Data select. This four-bit field is used to select which data is to be reported through the data register and

data-scale field. These bits return only 0000b, because the data register is not implemented.

PME enable. This bit returns a 0 when read because the PCI2050 does not support PME signaling.

7–2

Reserved. Bits 7–2 return 0s when read.

1–0

R/W

Power state. This two-bit field is used both to determine the current power state of a function and to set the function

into a new power state. The definition of this is given below:

00 – D0

01 – D1

10 – D2

11 – D3hot

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