PCI2050 datasheet(20/81 Pages) TI

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Table 2–6. Primary PCI Interface Control

TERMINAL

NAME

PDV

NO.

GHK

NO.

I/O

DESCRIPTION

P_DEVSEL

P11

I/O

Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As

a PCI initiator on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target

responds before time-out occurs, then the bridge terminates the cycle with an initiator abort.

P_FRAME

P10

I/O

Primary cycle frame. P_FRAME is driven by the initiator of a primary bus cycle. P_FRAME is asserted

to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.

When P_FRAME is deasserted, the primary bus transaction is in the final data phase.

P_GNT

Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access

to the primary PCI bus after the current data transaction has completed. P_GNT may or may not follow

a primary bus request, depending on the primary bus parking algorithm.

P_IDSEL

Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.

P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.

Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space

of the bridge can only be accessed from the primary bus.

P_IRDY

V11

I/O

Primary initiator ready. P_IRDY indicates ability of the primary bus initiator to complete the current data

phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY

and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are

inserted.

P_LOCK

V12

I/O

Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as an initiator.

P_PAR

R12

I/O

Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the

P_AD and P_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator

with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the

parity indicator of the initiator; a miscompare can result in a parity error assertion (P_PERR).

P_PERR

U12

I/O

Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated

parity does not match P_PAR when P_PERR is enabled through bit 6 of the command register.

P_REQ

Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as an

initiator.

P_SERR

P12

Primary system error. Output pulsed from the bridge when enabled through the command register

indicating a system error has occurred. The bridge needs not be the target of the primary PCI cycle

to assert this signal. When bit 6 is enabled in the bridge control register (offset 3Eh, see Section 4.32),

this signal also pulses indicating that a system error has occurred on one of the subordinate buses

downstream from the bridge.

P_STOP

R11

I/O

Primary cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current

primary bus transaction. This signal is used for target disconnects and is commonly asserted by target

devices which do not support burst data transfers.

P_TRDY

U11

I/O

Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current

data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both

P_IRDY and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are

inserted.

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