PCI2050 datasheet(30/81 Pages) TI

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bus grant terminals. Including the bridge, there are a total of ten potential secondary bus masters. These request and

grant signals are connected to the internal arbiter. When an external arbiter is implemented, S_REQ8–S_REQ1 and

S_GNT8–S_GNT1 are placed in a high impedance mode.

3.6.3

External Secondary Bus Arbitration

An external secondary bus arbiter can be used instead of the PCI2050 internal bus arbiter. When using an external

arbiter, the PCI2050 internal arbiter should be disabled by pulling S_CFN high.

When an external secondary bus arbiter is used, the PCI2050 internally reconfigures the S_REQ0 and S_GNT0

signals so that S_REQ0 becomes the secondary bus grant for the bridge and S_GNT0 becomes the secondary bus

request for the bridge. This is done because S_REQ0 is an input and can thus be used to provide the grant input to

the bridge, and S_GNT0 is an output and can thus provide the request output from the bridge.

When an external arbiter is used, all unused secondary bus grant outputs (S_GNT8–S_GNT1) are placed in a high

impedance mode. Any unused secondary bus request inputs (S_REQ8–S_REQ1) should be pulled high to prevent

the inputs from oscillating.

3.7

Decode Options

The PCI2050 supports positive decoding on the primary interface and negative decoding on the secondary interface.

Positive decoding is a method of address decoding in which a device responds only to accesses within an assigned

address range. Negative decoding is a method of address decoding in which a device responds only to accesses

outside of an assigned address range.

3.8

System Error Handling

The PCI2050 can be configured to signal a system error (SERR) for a variety of conditions. The P_SERR event

disable register (offset 64h, see Section 5.4) and the P_SERR status register (offset 6Ah, see Section 5.9) provide

control and status bits for each condition for which the bridge can signal SERR. These individual bits enable SERR

reporting for both downstream and upstream transactions.

By default, the PCI2050 will not signal SERR. If the PCI2050 is configured to signal SERR by setting bit 8 in the

command register (offset 04h, see Section 4.3), then the bridge signals SERR if any of the error conditions in the

P_SERR event disable register occur and that condition is enabled. By default, all error conditions are enabled in the

P_SERR event disable register. When the bridge signals SERR, bit 14 in the secondary status register (offset 1Eh,

see Section 4.19) is set.

3.8.1

Posted Write Parity Error

If bit 1 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0, then parity errors on the target bus

during a posted write are passed to the initiating bus as a SERR. When this occurs, bit 1 of the P_SERR status register

(offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.2

Posted Write Timeout

If bit 2 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while

attempting to complete a posted write, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 2

of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.3

Target Abort on Posted Writes

If bit 3 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the bridge receives a target abort

during a posted write transaction, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 3 of

the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

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