PCI2050 datasheet(19/81 Pages) TI

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Table 2–4. Primary PCI System

TERMINAL

NAME

PDV

NO.

GHK

NO.

I/O

DESCRIPTION

P_CLK

Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI

signals are sampled at rising edge of P_CLK.

P_RST

PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers

in a high–impedance state and reset all internal registers. When asserted, the device is completely

nonfunctional. During P_RST, the secondary interface is driven low. After P_RST is deasserted, the bridge

is in its default state.

Table 2–5. Primary PCI Address and Data

TERMINAL

NAME

PDV

NO.

GHK

NO.

I/O

DESCRIPTION

P_AD31

P_AD30

P_AD29

P_AD28

P_AD27

P_AD26

P_AD25

P_AD24

P_AD23

P_AD22

P_AD21

P_AD20

P_AD19

P_AD18

P_AD17

P_AD16

P_AD15

P_AD14

P_AD13

P_AD12

P_AD11

P_AD10

P_AD9

P_AD8

P_AD7

P_AD6

P_AD5

P_AD4

P_AD3

P_AD2

P_AD1

P_AD0

101

107

109

112

113

115

116

118

119

121

122

W10

V10

U13

W14

V14

U14

W15

V15

P15

R18

P18

N15

M14

N17

N19

M15

M18

M19

I/O

Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the

primary interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a

32-bit address or other destination information. During the data phase, P_AD31–P_AD0 contain data.

P_C/BE3

P_C/BE2

P_C/BE1

P_C/BE0

110

R10

V13

R19

I/O

Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.

During the address phase of a primary bus PCI cycle, P_C/BE3–P_C/BE0 define the bus command.

During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7–P_AD0),

P_C/BE1 applies to byte 1 (P_AD15–P_AD8), P_C/BE2 applies to byte 2 (P_AD23–P_AD16), and

P_C/BE3 applies to byte 3 (P_AD31–P_AD24).

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