PCI2050 datasheet(69/81 Pages) TI

69 / 81 page

5–13

5.18 Hot Swap Control Status Register

The hot swap control status register contains control and status information for CPCI hot swap resources.

Bit

Name

Hot swap control status

Type

R/W

Default

Hot swap control status

Type:

Read-only, Read/Write

Offset:

E6h

Default:

00h

Table 5–13. Hot Swap Control Status Register

BIT

TYPE

FUNCTION

ENUM insertion status. When set, the ENUM output is driven by the PCI2050. This bit defaults to 0, and will be set after

a PCI reset occurs, the pre-load of serial ROM is complete, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set

following an insertion when the board implementing the PCI2050 is ready for configuration. This bit cannot be set under

software control.

ENUM extraction status. When set, the ENUM output is driven by the PCI2050. This bit defaults to 0, and is set when the

ejector handle is opened and bit 7 is 0. Thus, this bit is set when the board implementing the PCI2050 is about to be removed.

This bit cannot be set under software control.

5–4

Reserved. Bits 5 and 4 return 0s when read.

R/W

LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HSLED) under normal conditions. However,

for a duration following a PCI_RST, the HSLED output is driven high by the PCI2050 and this bit will be ignored. When this

bit is interpreted, a 1 will cause HSLED high and a 0 will cause HSLED low.

Following PCI_RST, the HSLED output is driven high by the PCI2050 until the ejector handle is closed. When these

conditions are met, the HSLED is under software control via this bit.

Reserved. Bit 2 returns 0 when read.

R/W

ENUM interrupt mask. This bit allows the HSENUM output to be masked by software. Bits 6 and 7 are set independently

from this bit.

0 = Enable HSENUM output

1 = Mask HSENUM output

Reserved. Bit 0 returns 0 when read.

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