PCI2050 datasheet(27/81 Pages) TI

27 / 81 page

3–3

bridge does not recognize the configuration command. In this case, the bridge does not assert DEVSEL, and the

configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles

by accessing internal registers from the configuration header (see Table 4–1).

Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles

based on the bus number of the destination bus. The P_AD bus encoding during the address phase of a type 1 cycle

is shown in Figure 3–3. The device number and bus number fields define the destination bus and device for the cycle.

Reserved

Bus Number

Device

Number

Function

Number

Figure 3–3. PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle

Several bridge configuration registers shown in Table 4–1 are significant when decoding and claiming type 1

configuration cycles. The destination bus number encoded on the P_AD bus is compared to the values programmed

in the bridge configuration registers 18h, 19h, and 1Ah, which are the primary bus number, secondary bus number,

and subordinate bus number registers, respectively. These registers default to 00h and are programmed by host

software to reflect the bus hierarchy in the system (see Figure 3–4 for an example of a system bus hierarchy and how

the PCI2050 bus number registers would be programmed in this case).

When the PCI2050 claims a type 1 configuration cycle that has a bus number equal to its secondary bus number,

the PCI2050 converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the proper S_AD line

as the IDSEL (see Table 3–2). All other type 1 transactions that access a bus number greater than the bridge

secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration

cycles.

Table 3–2. PCI S_AD31–S_AD16 During the Address

Phase of a Type 0 Configuration Cycle

DEVICE

NUMBER

SECONDARY IDSEL

S_AD31–S_AD16

S_AD

ASSERTED

0000 0000 0000 0001

0000 0000 0000 0010

0000 0000 0000 0100

0000 0000 0000 1000

0000 0000 0001 0000

0000 0000 0010 0000

0000 0000 0100 0000

0000 0000 1000 0000

0000 0001 0000 0000

0000 0010 0000 0000

0000 0100 0000 0000

0000 1000 0000 0000

0001 0000 0000 0000

0010 0000 0000 0000

0100 0000 0000 0000

1000 0000 0000 0000

10h–1Eh

0000 0000 0000 0000

–

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