PCI2050 datasheet(50/81 Pages) TI

50 / 81 page

4–10

4.19 Secondary Status Register

The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its

bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective

bit.

Bit

Name

Secondary status

Type

R/W

Default

Secondary status

Type:

Read-only, read/write (see individual bit descriptions)

Offset:

1Eh

Default:

0200h

Table 4–4. Secondary Status Register

BIT

TYPE

FUNCTION

R/W

Detected parity error. Bit 15 is set when a parity error is detected on the secondary interface.

0 = No parity error detected on the secondary bus (default)

1 = Parity error detected on the secondary bus

R/W

Received system error. Bit 14 is set when the secondary interface detects S_SERR asserted. Note that the bridge never

asserts S_SERR.

0 = No S_SERR detected on the secondary bus (default)

1 = S_SERR detected on the secondary bus

R/W

Received master abort. Bit 13 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a

master abort.

0 = No master abort received (default)

1 = Bridge master aborted the cycle

R/W

Received target abort. Bit 12 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a target

abort.

0 = No target abort received (default)

1 = Bridge received a target abort

R/W

Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the secondary bus with a target abort.

0 = No target abort signaled (default)

1 = Bridge signaled a target abort

10–9

DEVSEL timing. These read-only bits encode the timing of S_DEVSEL and are hardwired to 01b, indicating that the bridge

asserts this signal at a medium speed.

R/W

Data parity error detected.

0 = The conditions for setting this bit have not been met

1 = A data parity error occurred and the following conditions were met:

a. S_PERR was asserted by any PCI device including the bridge.

b. The bridge was the bus master during the data parity error.

c. The parity error response bit (bit 1) is set in the bridge control register (offset 3Eh, see Section 4.32).

Fast back-to-back capable. Bit 7 is hardwired to 0.

User-definable feature (UDF) support. Bit 6 is hardwired to 0.

66 MHz capable. Bit 5 is hardwired to 0.

4–0

Reserved. Bits 4–0 return 0s when read.

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