PCI2050 datasheet(63/81 Pages) TI

63 / 81 page

5–7

5.8

Secondary Clock Control Register

The secondary clock control register is used to control the secondary clock outputs.

Bit

Name

Secondary clock control

Type

R/W

Default

Secondary clock control

Type:

Read-only, Read/Write

Offset:

68h

Default:

0000h

Table 5–8. Secondary Clock Control Register

BIT

TYPE

FUNCTION

Reserved. Bits 15 returns 0 when read.

R/W

Clockout10 disable.

0 = Clockout10 enabled (default).

1 = Clockout10 disabled and driven high.

R/W

Clockout9 disable.

0 = Clockout9 enabled (default).

1 = Clockout9 disabled and driven high.

R/W

Clockout8 disable.

0 = Clockout8 enabled (Default).

1 = Clockout8 disabled and driven high.

R/W

Clockout7 disable.

0 = Clockout7 enabled (default).

1 = Clockout7 disabled and driven high.

R/W

Clockout6 disable.

0 = Clockout6 enabled (default).

1 = Clockout6 disabled and driven high.

R/W

Clockout5 disable.

0 = Clockout5 enabled (default).

1 = Clockout5 disabled and driven high.

R/W

Clockout4 disable.

0 = Clockout4 enabled (default).

1 = Clockout4 disabled and driven high.

7–6

R/W

Clockout3 disable.

00, 01, 10 = Clockout3 enabled (00 is the default).

11 = Clockout3 disabled and driven high.

5–4

R/W

Clockout2 disable.

00, 01, 10 = Clockout2 enabled (00 is the default).

11 = Clockout2 disabled and driven high.

3–2

R/W

Clockout1 disable.

00, 01, 10 = Clockout1 enabled (00 is the default).

11 = Clockout1 disabled and driven high.

1–0

R/W

Clockout0 disable.

00, 01, 10 = Clockout0 enabled (00 is the default).

11 = Clockout0 disabled and driven high.

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