PCI2050 datasheet(45/81 Pages) TI

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4–5

4.5

Revision ID Register

The revision ID register indicates the silicon revision of the PCI2050.

Bit

Name

Revision ID

Type

Default

Revision ID

Type:

Read-only

Offset:

08h

Default:

00h (reflects the current revision of the silicon)

4.6

Class Code Register

This register categorizes the PCI2050 as a PCI-to-PCI bridge device (0604h) with a 00h programming interface.

Bit

Name

Class code

Base class

Sub class

Programming interface

Type

Default

Class code

Type:

Read-only

Offset:

09h

Default:

060400h

4.7

Cache Line Size Register

The cache line size register is programmed by host software to indicate the system cache line size needed by the

bridge on memory read line and memory read multiple transactions.

Bit

Name

Cache line size

Type

R/W

Default

Cache line size

Type:

Read/write

Offset:

0Ch

Default:

00h

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