PCI2050 datasheet(29/81 Pages) TI

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3–5

PCI2050

PCI

Device

S_CLKOUT3

PCI

Device

PCI

Device

PCI

Device

S_CLKOUT2

S_CLKOUT1

S_CLKOUT0

S_CLKOUT9

S_CLK

Figure 3–5. Secondary Clock Block Diagram

3.6

Bus Arbitration

The PCI2050 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary PCI bus arbitration.

Nine secondary bus requests and nine secondary bus grants are provided on the secondary of the PCI2050. Ten

potential initiators, including the bridge, can be located on the secondary bus. The PCI2050 provides a two-tier

arbitration scheme on the secondary bus for priority bus-master handling.

The two-tier arbitration scheme improves performance in systems in which master devices do not all require the same

bandwidth. Any master that requires frequent use of the bus can be programmed to be in the higher priority tier.

3.6.1

Primary Bus Arbitration

The PCI2050, acting as an initiator on the primary bus, asserts P_REQ when forwarding transactions upstream to

the primary bus. If a target disconnect, a target retry, or a target abort is received in response to a transaction initiated

on the primary bus by the PCI2050, then the device deasserts P_REQ for two PCI clock cycles.

When the primary bus arbiter asserts P_GNT in response to a P_REQ from the PCI2050, the device initiates a

transaction on the primary bus during the next PCI clock cycle after the primary bus is sampled idle.

When P_REQ is not asserted and the primary bus arbiter asserts P_GNT to the PCI2050, the device responds by

parking the P_AD31–P_AD0 bus, the C/BE3–C/BE0 bus, and primary parity (P_PAR) by driving them to valid logic

levels. If the PCI2050 is parking the primary bus and wants to initiate a transaction on the bus, then it can start the

transaction on the next PCI clock by asserting the primary cycle frame (P_FRAME) while P_GNT is still asserted. If

P_GNT is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction.

3.6.2

Internal Secondary Bus Arbitration

S_CFN controls the state of the secondary internal arbiter. The internal arbiter can be enabled by pulling S_CFN low

or disabled by pulling S_CFN high. The PCI2050 provides nine secondary bus request terminals and nine secondary

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