PCI2050 datasheet(46/81 Pages) TI

46 / 81 page

4–6

4.8

Primary Latency Timer Register

The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is

a primary PCI bus initiator and asserts P_FRAME, the latency timer begins counting from 0. If the latency timer expires

before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is

deasserted.

Bit

Name

Latency timer

Type

R/W

Default

Latency timer

Type:

Read/write

Offset:

0Dh

Default:

00h

4.9

Header Type Register

The header type register is read-only and returns 01h when read, indicating that the PCI2050 configuration space

adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h–3Fh of configuration space is

considered.

Bit

Name

Header type

Type

Default

Header type

Type:

Read-only

Offset:

0Eh

Default:

01h

4.10 BIST Register

The PCI2050 does not support built-in self test (BIST). The BIST register is read-only and returns the value 00h when

read.

Bit

Name

BIST

Type

Default

BIST

Type:

Read-only

Offset:

0Fh

Default:

00h

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