PCI2050 datasheet(11/81 Pages) TI

11 / 81 page

1–1

1 Introduction

1.1

Description

The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high performance connection path between two

peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets

on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge

supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act

independently.

The PCI2050 bridge is compliant with the

PCI Local Bus Specification, and can be used to overcome the electrical

loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The

PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with

an external secondary PCI bus arbiter.

The compact-PCI hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for

multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050 bridge is compliant with the

PCI-to-PCI Bridge Specification 1.1. The PCI 2050 provides compliance

for

PCI Power Management 1.0 and 1.1. The PCI2050 has been designed to lead the industry in power conservation.

An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates

up to 33 MHz.

1.2

Features

The PCI2050 supports the following features:

•

Configurable for

PCI Bus Power Management Interface Specification

•

Provides compact PCI hot-swap functionality

•

3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

•

Two 32-bit, 33-MHz PCI buses

•

Provides internal two-tier arbitration for up to nine secondary bus masters and supports an external

secondary bus arbiter

•

Burst data transfers with pipeline architecture to maximize data throughput in both directions

•

Independent read and write buffers for each direction

•

Up to three delayed transactions in both directions

•

Provides 10 secondary PCI clock outputs

•

Predictable latency per

PCI Local Bus Specification

•

Propagates bus locking

•

Secondary bus is driven low during reset

•

Provides VGA/palette memory and I/O, and subtractive decoding options

•

Advanced submicron, low-power CMOS technology

•

Packaged in 208-terminal QFP or 209-terminal MicroStar BGA

PCI2050 bảng dữ liệu(PDF) 11 Page - Texas Instruments

PCI2050 bảng dữ liệu(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

bảng dữ liệu tải về

Link URL