PCI2050 datasheet(48/81 Pages) TI

48 / 81 page

4–8

4.14 Secondary Bus Number Register

The secondary bus number register indicates the secondary bus number to which the bridge is connected. The

PCI2050 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to

determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles directed to the

secondary bus are converted to type 0 configuration cycles.

Bit

Name

Secondary bus number

Type

R/W

Default

Secondary bus number

Type:

Read/write

Offset:

19h

Default:

00h

4.15 Subordinate Bus Number Register

The subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus

existing behind the bridge. The PCI2050 uses this register, in conjunction with the primary bus number and secondary

bus number registers, to determine when to forward PCI configuration cycles to the subordinate buses. Configuration

cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses the bridge.

Bit

Name

Subordinate bus number

Type

R/W

Default

Subordinate bus number

Type:

Read/write

Offset:

1Ah

Default:

00h

4.16 Secondary Bus Latency Timer Register

The secondary bus latency timer specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge

is a secondary PCI bus initiator and asserts S_FRAME, the latency timer begins counting from 0. If the latency timer

expires before the bridge transaction has terminated, then the bridge terminates the transaction when its S_GNT is

deasserted. The PCI-to-PCI bridge S_GNT is an internal signal and is removed when another secondary bus master

arbitrates for the bus.

Bit

Name

Secondary bus latency timer

Type

R/W

Default

Secondary bus latency timer

Type:

Read/write

Offset:

1Bh

Default:

00h

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