PCI2050 datasheet(64/81 Pages) TI

64 / 81 page

5–8

5.9

P_SERR Status Register

The P_SERR status register indicates what caused a SERR event on the primary interface.

Bit

Name

P_SERR status

Type

R/W

Default

P_SERR status

Type:

Read-only

Offset:

6Ah

Default:

00h

Table 5–9. P_SERR Status Register

BIT

TYPE

FUNCTION

Reserved. Bit 7 returns 0 when read.

R/W

Master delayed read time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 224 retries on

a delayed read.

R/W

Master delayed write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 224 retries on

a delayed write.

R/W

Master abort on posted write transactions. A 1 indicates that P_SERR was signaled because of a master abort on a posted

write.

R/W

Target abort on posted writes. A 1 indicates that P_SERR was signaled because of a target abort on a posted write.

R/W

Master posted write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 224 retries on

a posted write.

R/W

Posted write parity error. A 1 indicates that P_SERR was signaled because of parity error on a posted write.

Reserved. Bit 0 returns 0 when read.

5.10 PM Capability ID Register

The capability ID register identifies the linked list item as the register for PCI power management. The capability ID

pointer and the value.

Bit

Name

Capability ID

Type

Default

Capability ID

Type:

Read-only

Offset:

DCh

Default:

01h

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