PCI2050 datasheet(41/81 Pages) TI

41 / 81 page

4–1

4 Bridge Configuration Header

The PCI2050 bridge is a single-function PCI device. The configuration header is in compliance with the

PCI-to-PCI

Bridge Architecture Specification 1.0. Table 4–1 shows the PCI configuration header, which includes the predefined

portion of the bridge’s configuration space. The PCI configuration offset is shown in the right column under the

OFFSET heading.

Table 4–1. Bridge Configuration Header

OFFSET

Device ID

Vendor ID

00h

Status

Command

04h

Class code

Revision ID

08h

BIST

Header type

Primary latency timer

Cache line size

0Ch

Base address 0

10h

Base address 1

14h

Secondary bus latency timer

Subordinate bus number

Secondary bus number

Primary bus number

18h

Secondary status

I/O limit

I/O base

1Ch

Memory limit

Memory base

20h

Prefetchable memory limit

Prefetchable memory base

24h

Prefetchable base upper 32 bits

28h

Prefetchable limit upper 32 bits

2Ch

I/O limit upper 16 bits

I/O base upper 16 bits

30h

Reserved

Capability pointer

34h

Expansion ROM base address

38h

Bridge control

Interrupt pin

Interrupt line

3Ch

Arbiter control

Extended diagnostic

Chip control

40h

Reserved

44h

Reserved

48h

Reserved

4Ch

Reserved

50h

Reserved

54h

Reserved

58h

Reserved

5Ch

Reserved

60h

GPIO input data

GPIO output enable

GPIO output data

P_SERR event disable

64h

Reserved

P_SERR status

Secondary clock control

68h

Reserved

6Ch–D8h

Power management capabilities

PM next item pointer

PM capability ID

DCh

Data

PMCSR bridge support

Power management control/status

E0h

Reserved

Hot swap control status

HS next item pointer

HS capability ID

E4h

Reserved

E8h–FFh

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