PCI2050 datasheet(24/81 Pages) TI

24 / 81 page

2–12

Table 2–11. JTAG Interface Terminals

TERMINAL

NAME

PDV

NO.

GHK

NO.

I/O

DESCRIPTION

TCLK

133

J19

JTAG boundary-scan clock. TCLK is the clock controlling the JTAG logic.

TDI

129

K18

JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the

JTAG interface. The new data on TDI is sampled on the rising edge of TCLK.

TDO

130

K17

JTAG serial data out. TDO is the serial output through which test instructions and data from the test

logic leave the PCI2050.

TMS

132

K14

JTAG test mode select. TMS causes state transitions in the test access port controller.

TRST

134

J18

JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter

a reset state and initialize the test logic.

Table 2–12. Power Supply

TERMINAL

DESCRIPTION

NAME

PDV NO.

GHK NO.

DESCRIPTION

GND

12, 20, 31, 37, 48, 52, 54,

59, 66, 72, 78, 86, 94, 100,

104, 111, 117, 123, 136,

142, 148, 156, 158, 160,

166, 174, 181, 187, 193,

199, 205

A6, A12, A14, B5, B10, C9,

C15, D19, F8, F13, F18,

G3, H15, J2, J14, L3, L19,

M6, N18, P6, P13, P14,

P17, T1, U5, U6, U10, V9,

W7, W12, W16

Device ground terminals

VCC

1, 26, 34, 40, 51, 53, 56, 62,

69, 75, 81, 91, 97, 103, 105,

108, 114, 120, 131, 139,

145, 151, 157, 163, 170,

178, 184, 190, 196, 202,

208

A4, A8, A13, A16, B7, C6,

C14, D1, E11, E19, F10,

G17, H18, K3, K15, M1,

M17, N2, N14, P7, P9, P19,

R3, R13, T19, U15, V8, W4,

W6, W11, W13

Power-supply terminal for core logic (3.3 V)

P_VCCP

124

L18

Primary bus-signaling environment supply. P_VCCP is used in

protection circuitry on primary bus I/O signals.

S_VCCP

135

J17

Secondary bus-signaling environment supply. S_VCCP is used in

protection circuitry on secondary bus I/O signals.

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