PCI2050 datasheet(65/81 Pages) TI

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5–9

5.11 PM Next Item Pointer Register

The PM next item pointer register is used to indicate the next item in the linked list of PCI power management

capabilities. The next item pointer returns E4h in compact PCI mode, indicating that the PCI2050 supports more than

one extended capability, but in all other modes returns 00h, indicating that only one extended capability is provided.

Bit

Name

Next item pointer

Type

Default

Next item pointer

Type:

Read-only

Offset:

DDh

Default:

E4h

CPCI mode

00h

All other modes

5.12 Power Management Capabilities Register

The power management capabilities register contains information on the capabilities of the PCI2050 functions related

to power management. The PCI2050 function supports D0, D1, D2, and D3 power states when MS1 is low. The

PCI2050 does not support any power states when MS1 is high.

Bit

Name

Power management capabilities

Type

Default

Power management capabilities

Type:

Read-only

Offset:

DEh

Default:

0602h or 0001h

Table 5–10. Power Management Capabilities Register

BIT

TYPE

FUNCTION

15–11

PME support. This five-bit field indicates the power states that the device supports asserting PME. A 0 for any of these bits

indicates that the PCI2050 cannot assert PME signal from that power state. For the PCI2050, these five bits return 00000b

when read indicating that PME is not supported.

D2 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D2 device power state. This

bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D2 device power state.

D1 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D1 device power state. This

bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D1 device power state.

8–6

Reserved. Bits 8–6 return 0s when read.

Device specific initialization. This bit returns 0 when read, indicating that the bridge function does not require special

initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it.

Auxiliary power source. This bit returns a 0 when read because the PCI2050 does not support PME signaling.

PMECLK. This bit returns a 0 when read because the PME signaling is not supported.

2–0

Version. This three-bit register returns the

PCI Bus Power Management Interface Specification revision.

001 = Revision 1.0, MS0 = 1

010 = Revision 1.1, MS0 = 0

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