PCI2050 datasheet(23/81 Pages) TI

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Table 2–9. Secondary PCI Interface Control

TERMINAL

NAME

PDV

NO.

GHK

NO.

I/O

DESCRIPTION

S_IRDY

177

C11

I/O

Secondary initiator ready. S_IRDY indicates the ability of the secondary bus initiator to complete the

current data phase of the transaction. A data phase is completed on a rising edge of S_PCLKn where

both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are

inserted.

S_LOCK

172

C12

I/O

Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as an

initiator.

S_PAR

168

C13

I/O

Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across

the S_AD and S_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity

indicator with a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared

to the initiator parity indicator. A miscompare can result in a parity error assertion (S_PERR).

S_PERR

171

E12

I/O

Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that

calculated parity does not match S_PAR when enabled through the command register.

S_REQ8

S_REQ7

S_REQ6

S_REQ5

S_REQ4

S_REQ3

S_REQ2

S_REQ1

S_REQ0

207

Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used

as inputs from secondary PCI bus initiators requesting the bus. Ten potential initiators (including the

bridge) can be located on the secondary PCI bus.

When the internal arbiter is disabled, the S_REQ0 signal is reconfigures as an external secondary bus

grant for the bridge.

S_SERR

169

B13

Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled

through the bridge control register. S_SERR is never asserted by the bridge.

S_STOP

173

B12

I/O

Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop the current

secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target

devices that do not support burst data transfers.

S_TRDY

176

B11

I/O

Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the

current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both

S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.

Table 2–10. Miscellaneous Terminals

TERMINAL

NAME

PDV

NO.

GHK

NO.

I/O

DESCRIPTION

BPCCE

Bus/power clock control management terminal. When signal BPCCE is tied high, and when the

PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus

in the B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When

tied low, placing the PCI2050 in the D3 power state has no effect on the secondary bus clocks.

GPIO3/HSSWITCH

GPIO2

GPIO1

GPIO0

General-purpose I/O pins

GPIO3 is HSSWITCH in CPCI mode.

HSSWITCH provides the status of the ejector handle switch to the CPCI logic.

HSENUM

127

L14

Hot swap ENUM

HSLED

128

K19

Hot swap LED output

MS0

155

E17

Mode select 0

MS1

106

R17

Mode select 1

102

125

R14

L17

These terminals have no function on the PCI2050.

S_M66ENA

153

E18

Secondary bus 66-MHz enable pin. This pin is always driven low to incicate that the secondary

bus speed is 33 MHz.

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