PCI2050 datasheet(67/81 Pages) TI

67 / 81 page

5–11

5.14 PMCSR Bridge Support Register

The PMCSR bridge support register is required for all PCI bridges and supports PCI-bridge-specific functionality.

Bit

Name

PMCSR bridge support

Type

Default

PMCSR bridge support

Type:

Read-only

Offset:

E2h

Default:

X0h

Table 5–12. PMCSR Bridge Support Register

BIT

TYPE

FUNCTION

Bus power control enable. This bit returns the value of the MS1/BCC input.

0 = Bus power/ clock control disabled.

1 = Bus power/clock control enabled.

B2/B3 support for D3hot. This bit returns the value of MS1/BCC input. When this bit is 1, the secondary clocks

are stopped when the device is placed in D3hot. When this bit is 0, the secondary clocks remain on in all device

states.

Note: If the primary clock is stopped, then the secondary clocks will stop because the primary clock is used to

generate the secondary clocks.

5–0

Reserved.

5.15 Data Register

The data register is an optional, 8-bit read–only register that provides a mechanism for the function to report

state-dependent operating data such as power consumed or heat dissipatin. The PCI2050 does not implement the

data register.

Bit

Name

Data

Type

Default

Data

Type:

Read-only

Offset:

E3h

Default:

00h

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