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FXLS93421 bảng dữ liệu(HTML) 103 Page - NXP Semiconductors |
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103 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Location Bit Address Register 7 6 5 4 3 2 1 0 $E6 USERDATA_6 PSI5_INIT2_D19 = 0, Channel 0 F9: D32 PSI5_INIT2_D19 = 1, Ch 0 F9: D32 = Ch 0 F9: D19 = Ch 1 F9: D19 Channel 0 F7: D14 $E7 USERDATA_7 Channel 0 F8: D16 Channel 0 F8: D16 = Channel 1 F8: D16 Channel 0 F8: D15 = Channel 1 F8: D15 $E8 USERDATA_8 Channel 0 F8: D18 Channel 0 F8: D18 = Channel 1 F8: D18 Channel 0 F8: D17 = Channel 1 F8: D17 $E9 USERDATA_9 Channel 1 F3: D5 Channel 1 F3: D4 $EA USERDATA_A Channel 1 F4: D7 Channel 1 F4: D6 $EB USERDATA_B Channel 1 F5: D9 Channel 1 F5: D8 $EC USERDATA_C Channel 1 F6: D11 Channel 1 F6: D10 $ED USERDATA_D Channel 1 F7: D13 Channel 1 F7: D12 $EE USERDATA_E PSI5_INIT2_D19 = 0, Channel 1 F9: D32 PSI5_INIT2_D19 = 1, Ch 1 F9: D32 = Ch 0 F9: D20 = Ch 1 F9: D20 Channel 1 F7: D14 Unprogrammed OTP Value 0 0 0 0 0 0 0 0 Table 192. PSI5 initialization phase 2 data transmissions of user data...continued 11.2.46 User data registers (USERDATA_10 - USERDATA_1E) User data registers are user programmable OTP registers which contain user-specific information. These registers are included in the user programmed OTP array error detection. These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode when ENDINIT is not set. See Section 11.2.10 for details on the register read process for these registers. Location Bit Address Register 7 6 5 4 3 2 1 0 $F0 USERDATA_10 USERDATA_10[7:0] $F1 USERDATA_11 USERDATA_11[7:0] $F2 USERDATA_12 USERDATA_12[7:0] $F3 USERDATA_13 USERDATA_13[7:0] $F4 USERDATA_14 USERDATA_14[7:0] $F5 USERDATA_15 USERDATA_15[7:0] $F6 USERDATA_16 USERDATA_16[7:0] $F7 USERDATA_17 USERDATA_17[7:0] $F8 USERDATA_18 USERDATA_18[7:0] $F9 USERDATA_19 USERDATA_19[7:0] $FA USERDATA_1A USERDATA_1A[7:0] $FB USERDATA_1B USERDATA_1B[7:0] $FC USERDATA_1C USERDATA_1C[7:0] $FD USERDATA_1D USERDATA_1D[7:0] $FE USERDATA_1E USERDATA_1E[7:0] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 Table 193. User data registers (USERDATA_10 - USERDATA_1E) 11.2.47 Lock and CRC registers The lock and CRC registers are automatically programmed OTP registers which include the lock bit, the block identifier, and the block OTP array CRC use for error detection. These registers are automatically programmed when the corresponding data array is programmed to OTP using the Write OTP Enable register as documented in Section 11.2.7. FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 103 / 254 |
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