FXLS93421 datasheet(63/254 Pages) NXP

63 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Asynchronous mode

Synchronous mode

Daisy chain mode

Dual transmission mode

Source ID

Source

ID enable

(SIDx_EN) Transmission

time

Transmission

data

Transmission

time[1]

Transmitted

data[2]

Transmission

time

Transmitted

data

Transmission

time

Transmitted

data

SOURCEID_

tASYNC

CH0_SNSDATA0

PDCM_RSPST0

CH0_SNSDATA0

See

Section 13.8

CH0_SNSDATA0

PDCM_

RSPST0

CH1_

SNSDATA0,

CH0_SNSDATA0

See

Section 13.7

SOURCEID_

PDCM_RSPST1

CH0_SNSDATA1

SOURCEID_

PDCM_RSPST2

CH1_SNSDATA0

See

Section 13.8

CH1_SNSDATA0

SOURCEID_

PDCM_RSPST3

CH1_SNSDATA1

Table 94. PSI5 source identification (SOURCEID_x)

[1]

See Section 11.2.18.1 "Periodic data collection mode response start time (PDCM_RSPSTx[12:0])"

[2]

See Section 11.2.25.2 "Channel data type 0 selection bits (CHxDATATYPE0)" and Section 11.2.25.3 "Channel data type 1 selection bits

(CHxDATATYPE1)"

In I2C mode, the SOURCEID_x registers are readable and writable. See Section 15.6.3,

for details regarding the effect of the SIDx_EN bits.

11.2.14 Communication timing register (TIMING_CFG)

The communication timing configuration register is a user programmed read/write

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$22

TIMING_CFG

PDCM_PER[2:0]

OSCTRAIN_

SEL

CK_CAL_RST

CRM_PER[1:0]

CK_CAL_EN

Unprogrammed OTP Value

Table 95. Communication timing register (TIMING_CFG)

11.2.14.1 Periodic data collection mode period (PDCM_PER[3:0])

The periodic data collection mode period selection bits set the data collection mode

period to be used by the DSI3, SPI, PSI5, or I2C master as shown in Table 96. This value

is only necessary for oscillator training and is only used if the CK_CAL_EN bit is set in

the TIMING_CFG register.

PDCM_PER[2] PDCM_PER[1] PDCM_PER[0]

Periodic data collection mode period

100 µs

125 µs

250 µs

333 µs

500 µs

800 µs

Table 96. Periodic data collection mode period (PDCM_PER[3:0])

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

63 / 254

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