FXLS93421 datasheet(46/254 Pages) NXP

46 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

DEVINIT

Condition

Normal operation

Device Initialization in Process

Table 54. Device initialization (DEVINIT)

11.2.2.9 VBUF under-voltage error (VBUFUV_ERR)

The VBUF under-voltage error bit is set if the VBUF voltage falls below the voltage

specified in Section 10.4. See Section 11.4 for details on the VBUF under-voltage monitor.

A common timer is used for all error bits in the DEVSTAT1 register. If any supply error

is present, the timer is reset to tUVOV_RCV. This bit is cleared based on the state of the

SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.

VBUFUV_ERR

Error condition

No error detected

VBUF Voltage Low

Table 55. VBUF under-voltage error (VBUFUV_ERR)

11.2.2.10 BUS IN under-voltage error (BUSINUV_ERR)

The BUS IN under-voltage error bit is set if the BUS_IN voltage falls below the voltage

specified in Section 10.4. See Section 11.4 for details on the BUS IN under-voltage

monitor. A common timer is used for all error bits in the DEVSTAT1 register. If any supply

error is present, the timer is reset to tUVOV_RCV. This bit is cleared based on the state of

the SUP_ER-R_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.

BUSINUV_ERR

Error condition

No error detected

BUS_IN Voltage Low

Table 56. BUS IN under-voltage error (BUSINUV_ERR)

11.2.2.11 VBUF over-voltage error (VBUFOV_ERR)

The VBUF over-voltage error bit is set if the VBUF voltage rises above the voltage

specified in Section 10.4. See Section 11.4 for details on the VBUF over-voltage monitor.

A common timer is used for all error bits in the DEVSTAT1 register. If any supply error

is present, the timer is reset to tUVOV_RCV. This bit is cleared based on the state of the

SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.

VBUFUV_ERR

Error condition

No error detected

VBUF Voltage High

Table 57. VBUF over-voltage error (VBUFOV_ERR)

11.2.2.12 Internal analog regulator voltage out of range error (INTREGA_ERR)

The internal analog regulator voltage out of range error bit is set if the internal analog

regulator voltage falls outside expected limits. A common timer is used for all error bits

in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV.

This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

46 / 254

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