FXLS93421 datasheet(69/254 Pages) NXP

69 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

OSCTRAIN_ERRCNT[2:0]

4 ms periods counted

before the OSCTRAIN

error flag is set

Minimum time for

error detection

(ms)

128

256

Table 109. Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])...continued

11.2.16.3 Capacitor test disable bit (CAPTEST_OFF)

The capacitor test disable bit provides the option to disable the VBUF capacitor test in

DSI3 mode as shown in Table 110.

CAPTEST_OFF Capacitor test status

Capacitor test is operational as specified in Section 11.4.1

Capacitor test will not run

Table 110. Capacitor test disable bit (CAPTEST_OFF)

If a capacitor error is present, the VBUFUV_ERR bit is set in the DEVSTAT1 register as

specified in Section 11.4.1. The presence of the VBUFUV_ERR will prevent the user from

writing to the TIMING_CFG2 register to disable the capacitor test unless and until the

capacitor error recovers.

In SPI and I2C mode, the CAPTEST_OFF bit is readable and writable, but has no impact

on device operation or performance.

In PSI5 mode, the CAPTEST_OFF bit is readable and writable, but has no impact on

device operation or performance.

11.2.16.4 Background diagnostic mode fragment size (BDM_FRAGSIZE)

The background diagnostic mode fragment size bit sets the number of background

diagnostic command bits and response chips to be sent per Periodic Data Collection

Mode sampling period.

BDM_

FRAGSIZE

BDM command fragment size

(Bits)

BDM response fragment size

(Chips)

Table 111. Background diagnostic mode fragment size (BDM_FRAGSIZE)

In SPI and I2C mode, the BDM_FRAGSIZE bit is readable and writable, but has no

impact on device operation or performance.

In PSI5 mode, the BDM_FRAGSIZE bit is readable and writable, but has no impact on

device operation or performance.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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