FXLS93421 datasheet(75/254 Pages) NXP

75 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

ASYNC bit

SOURCEID

Transmitted data

Time slot

start time

Default start (PDCM_

RSPSTx[12:0] = 0x00)

SOURCEID_0

CH0_SNSDATA0

PDCM_

RSPST0[12:0]

Transmit Data with a start time of 20 µs

SOURCEID_1

CH0_SNSDATA1

PDCM_

RSPST1[12:0]

Transmit Data with a start time of 20 µs

SOURCEID_2

CH1_SNSDATA0

PDCM_

RSPST2[12:0]

Transmit Data with a start time of 20 µs

SOURCEID_3

CH1_SNSDATA1

PDCM_

RSPST3[12:0]

Transmit Data with a start time of 20 µs

Table 124. Asynchronous mode: Source ID response start time...continued

In SPI and I2C mode, the PDCM_RSPSTx registers are readable and writable, but have

no impact on device operation or performance.

11.2.18.2 Broadcast read command type selection bits (BRC_RSP[1:0])

The broadcast read command type selection bits select the broadcast read command

types that the device responds to for each Source ID as shown in Table 125:

BRC_RSP[1]

BRC_RSP[0]

Response

Respond to all Broadcast Read Commands

Respond to Broadcast Read Command 0 only

Respond to Broadcast Read Command 1 only

Respond to all Broadcast Read Commands

Table 125. Broadcast read command type selection bits (BRC_RSP[1:0])

If a device is programmed to respond only to BRC0 or BRC1 commands, it will

synchronize to alternate responses when BDM commands are received.

• If the last command prior to a BDM command is a BRC0, a device programmed to

respond only to BRC0 commands will not respond to the first BDM command and will

then respond to every other BDM command until the next BRC command is received.

• If the last command prior to a BDM command is a BRC0, a device programmed to

respond only to BRC1 commands will respond to the first BDM command, and will then

response to every other BDM command until the next BRC command is received.

• If the last command prior to a BDM command is a BRC1, a device programmed to

respond only to BRC0 commands will respond to the first BDM command, and will then

response to every other BDM command until the next BRC command is received.

• If the last command prior to a BDM command is a BRC1, a device programmed to

respond only to BRC1 commands will not respond to the first BDM command and will

then respond to every other BDM command until the next BRC command is received.

In PSI5 mode, the BRC_RSP[1:0] bits are readable and writable, but have no impact on

device operation or performance.

In SPI and I2C mode, the BRC_RSP[1:0] bits are readable and writable, but have no

impact on device operation or performance.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

75 / 254

FXLS93421 bảng dữ liệu(PDF) 75 Page - NXP Semiconductors

FXLS93421 bảng dữ liệu(HTML) 75 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL