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FXLS93421 bảng dữ liệu(PDF) 45 Page - NXP Semiconductors

tên linh kiện FXLS93421
Giải thích chi tiết về linh kiện  Dual channel inertial sensor
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FXLS93421 bảng dữ liệu(HTML) 45 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
timer is decremented until it reaches zero. This error is cleared based on the state of the
SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Table 51.
SUP_
ERR_DIS
DSI3 and SPI operating modes
(COMMTYPE =0, 2, 3 and 4)
PSI5 operating modes
(COMMTYPE =1 and 5)
I2C operating modes
(COMMTYPE =6, 7)
0
No Response until the supply
monitor timer expires. The
Sensor Data Field Error Code is
transmitted for one response after
the supply monitor timer expires.
A read of the DEVSTAT1 register
clears all supply errors, using any
communication interface or on a
data transmission that includes the
error in the status field, if and only if
the timer has reached zero.
1
No transmissions occur if the timer
is non-zero. The error is cleared
when the timer reaches zero and
normal transmissions resume.
No transmissions occur if the timer
is non-zero. The error is cleared
when the timer reaches zero and
normal transmissions resume.
No response until the supply
monitor timer expires.
A read of the DEVSTAT1 register
clears all supply errors.
Table 51. Supply error flag (SUPPLY_ERR)
11.2.2.6 Test mode (TESTMODE)
The test mode bit is set if the device is in test mode. The TESTMODE bit can be cleared
by a test mode operation or by a power cycle.
TESTMODE
Operating mode
0
Test mode is not active
1
Test mode is active
Table 52. Test mode (TESTMODE)
11.2.2.7 Device reset (DEVRES)
The device reset bit is set following a device reset. This error is cleared by a read of the
DEVSTAT register through any communication interface or on a data transmission that
includes the error in the status field.
DEVRES
Error condition
0
Normal operation
1
Device reset occurred
Table 53. Device reset (DEVRES)
11.2.2.8 Device initialization (DEVINIT)
The device initialization bit is set following either a device reset or a change to any of the
following bits: CHx_CFG_U1[7:2] or CHx_CFG_U3[1:0]. The bit is cleared once sensor
data is valid for read through one of the device communication inter-faces (tPOR_DataValid).
Note: Some LPF selections have a step response time longer than the tPOR_DataValid
delay. If any of these filters are used, the filter may not have achieved the final value once
DEVINIT is cleared.
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
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