FXLS93421 datasheet(87/254 Pages) NXP

87 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

ARM_

CFG[2]

ARM_

CFG[1]

ARM_

CFG[0]

PCM

Operating mode

Output type

Reference

Moving Average

Mode

Open-Drain, Active Low with

Pull-up Current

Section 11.9.1

Count Mode

Open-Drain, Active High with

Pull-down Current

Section 11.9.2

Count Mode

Open-Drain, Active Low with

Pull-up Current

Section 11.9.2

Unfiltered Mode

Open-Drain, Active High with

Pull-down Current

Section 11.9.3

Unfiltered Mode

Open-Drain, Active Low with

Pull-up Current

Section 11.9.3

Table 151. Arming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)...continued

Note: The arming function is reset on a change to the ARM_CFG bits. This includes the

downsampling state and all history registers.

When the PCM output is enabled, a Pulse Code Modulated signal proportional to the

data selected by the DATATYPE0 selection bits is output on the ARM/PCM pin. See

Section 11.8 for more information regarding the PCM output.

11.2.27 Channel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5,

CH1_CFG_U5)

The Channel 0 and Channel 1 user configuration #5 registers are user programmable

read/write registers which contain channel-specific configuration information. These

registers are included in the read/write array error detection.

These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$44

CH0_CFG_U5

ST_CTRL[3:0]

OC_LIMIT[2:0]

DSP_DIS

$4C

CH1_CFG_U5

ST_CTRL[3:0]

OC_LIMIT[2:0]

DSP_DIS

Unprogrammed OTP Value

Table 152. Channel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5, CH1_CFG_U5)

11.2.27.1 Self-test control bits (ST_CTRL[3:0])

The self-test control bits select one of the various analog and digital self-test features of

the device as shown in Table 153.

The self-test control bits are writable in DSI3 command and response mode.

The self-test control bits are writable in SPI Mode.

The self-test control bits are writable in I2C Mode.

The self-test control bits are writable in PSI5 programming mode.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

87 / 254

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