FXLS93421 datasheet(30/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

10.13 Dynamic electrical characteristics - SPI

VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified

Characteristic

Symbol

Min

Typ

Max

Units

Test

notes

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10794

Clock (SCLK) period (10 % of VCC to 10 % of VCC)

tSCLK

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10801

Clock (SCLK) high time (90 % of VCC to 90 % of VCC)

tSCLKH

—

10802

Clock (SCLK) low time (10 % of VCC to 10 % of VCC)

tSCLKL

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10800

Clock (SCLK) rise time (10 % of VCC to 90 % of VCC)

tSCLKR

—

10803

Clock (SCLK) fall time (90 % of VCC to 10 % of VCC)

tSCLKF

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10799

SS_B asserted to SCLK high (SS_B = 10 % of VCC to SCLK = 10 % of

VCC)

tLEAD

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10798

SS_B asserted to MISO valid (SS_B = 10 % of VCC to MISO = 10/90 %

of VCC)

tACCESS

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10797

Data setup time (MOSI = 10/90 % of VCC to SCLK = 10 % of VCC)

tSETUP

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10796

MOSI Data hold time (SCLK = 90 % of VCC to MOSI = 10/90 % of VCC)

tHOLD_IN

—

10804

MISO Data hold time (SCLK = 90 % of VCC to MISO = 10/90 % of VCC)

tHOLD_OUT

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10795

SCLK low to data valid (SCLK = 10 % of VCC to MISO = 10/90 % of

VCC)

tVALID

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10807

SCLK low to SS_B high (SCLK = 10 % of VCC to SS_B = 90 % of VCC)

tLAG

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10806

SS_B high to MISO disable (SS_B = 90 % of VCC to MISO = High Z)

tDISABLE

—

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

SS_B high to SS_B low (SS_B = 90 % of VCC to SS_B = 90 % of VCC)

10805

Following Sensor Data Request Commands

tSSN_SENSE

500

—

10813

Following Register Reads/Writes Registers

tSSN_R

500

—

10812

Following Register Write to the UF_REGION_W Register

tSSN_UF01

—

µs

10810

Time Between Sensor Data Requests (Same Channel, SPI Only, Arm

Enabled)

tACC_REQ_x

—

µs

Arming Output Activation Time (ARM0, ARM1, IARM = 200 µA)

10809

Moving Average and Count Arming Modes

tARM

—

1.50

µs

10817

Unfiltered Mode Activation Delay

tARM_UF_DLY

—

1.50

µs

10816

Unfiltered Mode Arm Assertion Time

tARM_UF_ASSERT

5.00

—

6.00

µs

Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)

10808

SCLK low to SS_B low (SCLK = 10 % of VCC to SS_B = 90 % of VCC)

tCLKSS

—

Table 36. Dynamic electrical characteristics - SPI

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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