FXLS93421 datasheet(72/254 Pages) NXP

72 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

In DSI3 mode, the DUALTRANS mode is readable and writable, but has no impact on

device operation or performance.

In SPI and I2C mode, the DUALTRANS bits are readable and writable, but has no impact

on device operation or performance.

11.2.17.5 Error message information extension bit (EMSG_EXT)

In PSI5 mode, the error message information extension bit enables or disables additional

PSI5 error message information as shown in Table 118.

EMSG_EXT Description

All internal Errors map to 0x1F4 (See Section 13.3.4)

Additional PSI5 reserved codes are used for internal error distinction (See

Section 13.3.4)

Table 118. Error message information extension bit (EMSG_EXT)

In DSI3 mode, the EMSG_EXT bit is readable and writable, but has no impact on device

operation or performance.

In SPI and I2C mode, the EMSG_EXT bit is readable and writable, but has no impact on

device operation or performance.

11.2.17.6 PSI5 response message error detection selection bit (P_CRC)

In PSI5 mode, the response message error detection selection bit selects either

even parity, or a 3-bit CRC for error detection of the PSI5 response message. See

Section 11.2.18.1 for details regarding response message error detection.

P_CRC

Parity or CRC

Parity

CRC

Table 119. PSI5 response message error detection selection bit (P_CRC)

In DSI3 mode, the P_CRC bit is readable and writable, but has no impact on device

operation or performance.

In SPI and I2C mode, the P_CRC bit is readable and writable, but has no impact on

device operation or performance.

11.2.17.7 Initialization phase 2 data extension bit (INIT2_EXT)

In PSI5 mode, the initialization phase 2 data extension bit enables or disables data

transmission in data fields D33 through D48 of PSI5 initialization phase 2 as shown in

Table 120.

INIT2_EXT

Description

D33 through D48 are not transmitted

D33 through D48 are transmitted as defined in Section 13.4.2.1

Table 120. Initialization phase 2 data extension bit (INIT2_EXT)

In DSI3 mode, the INIT2_EXT bit is readable and writable, but has no impact on device

operation or performance.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

72 / 254

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