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FXLS93421 bảng dữ liệu(PDF) 12 Page - NXP Semiconductors |
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FXLS93421 bảng dữ liệu(HTML) 12 Page - NXP Semiconductors |
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12 / 254 page ![]() NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 9.3 Pinning: DSI3 or PSI5 mode BUSSW_L BUS_O TEST5 TEST1 TEST_MOSI TEST4 TEST_MISO TEST_SCLK 4 5 3 2 1 9 10 11 12 6 7 8 16 17 15 14 13 Transparent topview FXLS9xxxx terminal 1 index area aaa-030598 Figure 10. Device pinout: DSI3 or PSI5 mode pinout 9.4 Pin description: DSI3 or PSI5 mode Pin Pin Name Definition Description 1 BUS_O Supply Out This pin is connected to the IDATA pin through an internal sense resistor and provides the supply connection to the next slave in a daisy chain configuration. In DSI3 mode, an external capacitor must be connected between this pin and VSS as shown in Figure 2. In PSI5 mode, NXP recommends that this pin be unterminated. Optionally, this pin can be connected to IDATA. 2, 4, 6, 12 TEST Test Pin NXP recommends that these pins be unterminated. Optionally, this pin can be tied to VSS. 3, 5 BUSSW_L Low Side Bus Switch Driver In PSI5 daisy chain mode, these pins are connected to the gate of an N- channel FET which connects BUSRTN to the next slave in the daisy chain. An external pulldown resistor is required on the gate of the N-channel FET as shown in Figure 4. Note: both pins provide the identical function. It is necessary to connect only one pin is to the bus switch gate. If unused, or in DSI3 mode, NXP recommends that this pin be unterminated. Optionally, this pin can be tied to VSS. 7, 14 BUSRTN/VSS Supply Return This pin is the supply return node. 8 TEST_SS_B Slave select NXP recommends that this pin be unterminated. Optionally, this pin can be connected to VBUF. 9 TEST_SCLK SPI Clock NXP recommends that this pin be unterminated. Optionally, this pin can be connected to VSS. 10 TEST_MOSI SPI Data In NXP recommends that this pin be unterminated. Optionally, this pin can be connected to VSS. 11 TEST_MISO SPI Data Out This pin must be left unconnected. Table 10. Device pinout: DSI3 or PSI5 mode pinout FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 12 / 254 |
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