FXLS93421 datasheet(85/254 Pages) NXP

85 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Data transmitted

CHxDATA

TYPE1[2]

CHxDATA

TYPE1[1]

CHxDATA

TYPE1[0]

Data transmitted

Offset

canceled?

Moving

average?

Interpolation?

Temperature Sensor Data (As specified in Section 11.7.2)

Table 146. Channel data type 1 selection bits (CHxDATATYPE1)...continued

11.2.25.4 Signal chain moving average selection bits (MOVEAVG[1:0])

The signal chain moving average selection bits determine the input sample period to be

used for the signal chain moving average filter.

MOVEAVG[1] MOVEAVG[0]

Typical signal

sampling period

(Dependent on oscillator)

(µs)

Signal chain

moving average

Interpolation

Determined by LPF

Bypassed

Enabled

8 Sample Moving Average

Disabled

8 Sample Moving Average

Disabled

128

8 Sample Moving Average

Disabled

Table 147. Signal chain moving average selection bits (MOVEAVG[1:0])

Changes to these register bits reset the DSP data path. The contents of the SNSDATA_x

registers are not guaranteed until the DSP has completed initialization as specified in

Section 10.20. Reads of the SNSDATA_x registers and Sensor Data requests should be

prevented during this time.

11.2.26 Channel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4,

CH1_CFG_U4)

The Channel 0 and Channel 1 user configuration #4 registers are user programmable

read/write registers which contain channel-specific configuration information. These

registers are included in the read/write array error detection.

These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$43

CH0_CFG_U4

RESET_OC

INVERT

OC_FILT[1:0]

PCM

ARM_CFG[2:0]

$4B

CH1_CFG_U4

RESET_OC

INVERT

OC_FILT[1:0]

PCM

ARM_CFG[2:0]

Unprogrammed OTP Value

Table 148. Channel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4, CH1_CFG_U4)

11.2.26.1 Reset offset cancellation startup bit (RESET_OC)

When the reset offset cancellation startup bit is written to logic 1, the offset cancellation

startup is forced to phase 0 and follows the phase advancement as documented in

Section 11.6.4.6. The RESET_OC bit is cleared when the offset cancellation phase

reaches phase 1.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

85 / 254

FXLS93421 bảng dữ liệu(PDF) 85 Page - NXP Semiconductors

FXLS93421 bảng dữ liệu(HTML) 85 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL