FXLS93421 datasheet(76/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.19 DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)

The DSI3 and PSI5 command blocking registers are user programmed read/write

registers which contain user-specific con-figuration information for DSI3 mode and PSI5

mode. These registers are included in the read/write array error detection.

These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

programming mode.

Location

Bit

Address

$38

PDCM_

CMD_B_L

PDCM_CMD_B[7:0]

$39

PDCM_

CMD_B_H

RESERVED

PDCM_CMD_B[12:8]

Unprogrammed OTP Value

Table 126. DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)

In DSI3 mode, the DSI3 periodic data collection mode command blocking time bits

set the periodic data collection mode command blocking time in 1.0 µs increments,

with zero as the default value of 450 µs. For proper communication, the command

blocking time must exceed the completion of the last source response transmission. See

Section 12.1.1 for details regarding the command receiver and command blocking.

Care must be taken to prevent from programming command blocking times which

prevent proper command decoding in the system and to ensure proper sampling of the

VHIGH voltage. As shown in Section 12.1.1, Figure 63, the VHIGH voltage is initially

captured at the end of the command blocking time and then filtered. The user must

ensure that the command blocking end time is set for a time when no command or

response transmissions are occurring to provide the most stable BUS_I voltage.

PDCM_CMD_B[12:0] Sync pulse blocking time

450 µs

Non-Zero

Sync Pulse Blocking Time = PDCM_CMD_B x 1 µs

Table 127. DSI3 mode: Command blocking time bits

In PSI5 mode, the command blocking time bits set the PSI5 sync pulse blocking time in

1.0 µs increments, with zero as the default value of 450 µs. See Section 13.2.1 for details

regarding the PSI5 sync pulse receiver and command blocking.

Care must be taken to prevent from programming command blocking times which

prevent proper sync pulse decoding in the system and to ensure proper sampling of the

PSI5 voltage.

PDCM_CMD_B[12:0] Sync pulse blocking time

0, 1, 2, 3, 4, 5, 6, 7, 8, 9 450 µs

10 - 8191

Sync Pulse Blocking Time = PDCM_CMD_B x 1 µs

Table 128. PSI5 mode: Command blocking time bits

In SPI and I2C mode, the PDCM_CMD_B bits are readable and writable, but have no

impact on device operation or performance.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

76 / 254

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