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FXLS93421 bảng dữ liệu(PDF) 31 Page - NXP Semiconductors |
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FXLS93421 bảng dữ liệu(HTML) 31 Page - NXP Semiconductors |
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31 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units Test notes Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ) 10815 SS_B high to SCLK high (SS_B = 90 % of VCC to SCLK = 90 % of VCC) tSSCLK 50 — — ns 7 10818 SPI Data Latency tLAT_SPI — — 1 µs 7, 8 Pin Capacitance (MISO, MOSI, SCLK, SS_B to VSS) CSPI_PIN — — 10 pF 7 Table 36. Dynamic electrical characteristics - SPI...continued 10.14 Dynamic electrical characteristics - I2C VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units Test notes Clock (SCL) Period (30 % of VCC to 30 % of VCC) 10819 100 kHz Mode tSCLK_100 9.50 — — µs 6 10820 400 kHz Mode tSCLK_400 2.37 — — µs 6 10821 1000 kHz Mode tSCLK_1000 1.00 — — µs 6 Clock (SCL) High Time (70 % of VCC to 70 % of VCC) 10823 100 kHz Mode tSCLH_100 4.00 — — µs 6 10837 400 kHz Mode tSCLH_400 0.60 — — µs 6 10836 1000 kHz Mode (note: not compliant with UM10204[1] tSCLH_1000 0.50 — — µs 6 Clock (SCL) Low Time (30 % of VCC to 30 % of VCC) 10835 100 kHz Mode tSCLL_100 4.70 — — µs 6 10839 400 kHz Mode tSCLL_400 1.30 — — µs 6 10838 1000 kHz Mode tSCLL_1000 0.50 — — µs 6 Clock (SCL) and Data (SDA) Rise Time (30 % of VCC to 70 % of VCC) 10834 100 kHz Mode tSRISE_100 — — 1000 ns 6 10841 400 kHz Mode tSRISE_400 — — 300 ns 6 10840 1000 kHz Mode tSRISE_1000 — — 120 ns 6 Clock (SCL) and Data (SDA) Fall Time (70 % of VCC to 30 % of VCC) 10833 100 kHz Mode tSFALL_100 — — 300 ns 6 10844 400 kHz Mode tSFALL_400 — — 300 ns 6 10843 1000 kHz Mode tSFALL_1000 — — 120 ns 6 Data Input Setup Time (SDA = 30/70 % of VCC to SCL = 30 % of VCC) 10832 100 kHz Mode tSETUP_100 250 — — ns 6 10846 400 kHz Mode tSETUP_400 100 — — ns 6 10845 1000 kHz Mode tSETUP_1000 50 — — ns 6 Data Input Hold Time (SCL = 70 % of VCC to SDA = 30/70 % of VCC) 10831 100 kHz Mode tHOLD_100 0 — 900 ns 6 10848 400 kHz Mode tHOLD_400 0 — 900 ns 6 10847 1000 kHz Mode tHOLD_1000 0 — 300 ns 6 Table 37. Dynamic electrical characteristics - I2C FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 31 / 254 |
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