FXLS93421 datasheet(5/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

6.2 PSI5 application diagrams

6.2.1 PSI5 parallel or universal mode application diagram

VBUF

IDATA

VSS

VCC

VCE

VSS

aaa-030556

Figure 3. PSI5 parallel or universal mode application diagram

Ref

Des

Type

Description

Component value selection and range

Purpose

General

purpose

82 Ω, 5 %,

200 PPM

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

For proper device function, the minimum value

can be 0 Ω. The maximum value is determined

by the minimum bus voltage provided at the

module pin and the minimum operating voltage of

the device. To meet the minimum PSI5 operating

voltage at the module pin, the maximum

resistance including all tolerances is 89.0 Ω.[1]

VCC filtering and signal damping

General

purpose

27 Ω, 5 %,

200 PPM

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

For proper device function, the minimum value

can be 0 Ω. The maximum value is determined

by the minimum bus voltage provided at the

module pin. To meet the minimum PSI5 operating

voltage at the module pin, the maximum

resistance including all tolerances is 66.6 Ω. If

the low response current is used, the maximum

resistance including all tolerances is 133 Ω.

IDATA filtering and signal damping

Ceramic

2.2 nF, 10

%, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing

VCC power supply decoupling and signal

damping. For optimal EMC performance, this

component is to be placed as close to the BUS_I

and BUSRTN connector pins as possible.

Ceramic

15 nF, 10

%, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing[2]

VCC power supply decoupling. For optimal EMC

performance, this component is to be placed

as close to the BUS_I and BUSRTN pins as

possible.

Ceramic

470 pF, 10

%, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing

IDATA Filtering and Signal Damping

Table 4. PSI5 parallel or universal mode external component recommendations

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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