FXLS93421 datasheet(57/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

If the bit is set from SPI mode, the process occurs once the PSI5_TEST bit is set with no

SPI reply necessary.

If the bit is set from I2C mode, the process occurs once the PSI5_TEST bit is set with no

I2C reply necessary.

If PSI5 mode is enabled in the COMMTYPE register, this bit has no impact on device

operation or performance.

11.2.10 UF region selection registers (UF_REGION_x)

The UF region load register is a user read/write register that contains the control bits for

the UF0 and UF1 regions to be accessed. This register is included in the user read/write

array error detection. The UF region active register is a read-only register that contains

the status bits for the UF0 and UF1 regions to be accessed.

The UF_REGION_W register is readable and writable in DSI3 mode, SPI mode, I2C

mode or PSI5 Programming Mode. The UF_REGION_R register is readable in DSI3

mode, SPI mode, I2C mode or PSI5 Programming Mode.

Location

Bit

Address

$14

UF_

REGION_W

REGION_LOAD[3:0]

$15

UF_REGION_R

REGION_ACTIVE[3:0]

Reset Value

Table 82. UF region selection registers (UF_REGION_x)

The user OTP regions UF0, UF1, and F share a block of 16 registers. Prior to reading the

registers via any communication interface, the user must ensure that the desired OTP

registers are loaded into the readable registers. To ensure proper reading of the UF0,

UF1 and F registers, follow this procedure:

1. Write the desired address range to be read to the REGION_LOAD[3:0] bits in the

UF_REGION_W register using one of the communication interfaces available via the

COMMTYPE register.

REGION_LOAD[3:0]

OTP register addresses loaded into the readable

registers

Not Applicable

0010 through 1001

RESERVED

Address Range $A0 through $AF

Address Range $B0 through $BF

Address Range $C0 through $CF

Address Range $D0 through $DF

Address Range $E0 through $EF

Address Range $F0 through $FF

Table 83. Region load bits

2. Delay a minimum of tSSN_UF01.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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