FXLS93421 datasheet(4/254 Pages) NXP

4 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

6 Application diagrams

6.1 DSI3 application diagrams

6.1.1 DSI3 discovery mode application diagram

VBUF

VSS

BUS_I

Optional

Bus Termination

BUSRTN

IDATA

BUS_O

BUSIN

BUSRTN

BUSOUT

aaa-030552

Figure 2. DSI3 discovery mode application diagram

Ref

Des

Type

Typical value

description

Component value selection and range

Comment

General

purpose

330 Ω, 5 %,

200 PPM

The system level communication, EMC, and

ESD testing determine the optimal value of this

component.

Optional bus termination for high inductance bus

wire connections. For optimal EMC performance,

this component along with C4 are to be placed as

close to the BUS_I and BUSRTN connector pins

as possible.

Ceramic

220 pF,

10 %, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

For optimal EMC performance, this component

along with R1 are to be placed as close to the

BUS_I and BUSRTN connector pins as possible.

Ceramic

0.47 µF,

10 %, 10 V

minimum,

X7R

The optimal value of this component should be

determined based on the system level micro-cut

immunity requirement. To achieve the specified

power supply rejection, the minimum value

including all tolerances is 0.22 µF. The maximum

specified value including all tolerances is 2 µF.

For optimal EMC performance, this component is

to be placed as close to the VBUF and BUSRTN

pins as possible.

Ceramic

100 pF,

10 %, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

For optimal EMC performance, this component

is to be placed as close to the BUS_O and

BUSRTN connector pins as possible.

Ceramic

2.2 nF,

10 %, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

Optional bus termination for high inductance bus

wire connections. For optimal EMC performance,

this component along with R1 are to be placed as

close to the BUS_I and BUSRTN connector pins

as possible.

Note:

The total bus capacitance must not exceed the values specified in the DSI3[2] standard.

The external components are dependent on the bus master and bus impedance and may vary from application to application.

Table 3. DSI3 discovery mode external component recommendations

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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