FXLS93421 datasheet(70/254 Pages) NXP

70 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.16.5 Background diagnostic mode enable (BDM_EN)

The background diagnostic mode enable bit enables background diagnostic mode as

described in Table 112. See Section 12.4 for details regarding background diagnostic

mode.

BDM_EN

Background diagnostic mode

Disabled

Enabled

Table 112. Background diagnostic mode enable (BDM_EN)

In SPI and I2C mode, the BDM_EN bit is readable and writable, but has no impact on

device operation or performance.

In PSI5 mode, the BDM_EN bit is readable and writable, but has no impact on device

operation or performance.

11.2.17 PSI5 configuration register (PSI5_CFG)

The PSI5 configuration register is a user programmable OTP register that contains PSI5

specific configuration information. This register is included in the read/write array error

detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

programming mode.

Location

Bit

Address

$25

PSI5_CFG

SYNC_PD

DAISY_CHAIN

PSI5_ILOW

DUALTRANS

EMSG_EXT

P_CRC

INIT2_EXT

ASYNC

Unprogrammed OTP Value

FXLS93xxx

Unprogrammed

Default PSI5 Mode

Table 113. PSI5 configuration register (PSI5_CFG)

11.2.17.1 Sync pulse pull-down enable bit (SYNC_PD)

In PSI5 mode, the sync pulse pull-down enable bit selects if the Sync pulse pull-down

is enabled once a sync pulse is detected. See Section 11.2.18.1 for more information

regarding the sync pulse pulldown.

SYNC_PD

Sync pulse pull-down

Disabled

Enabled for all PSI5 operating modes

Table 114. Sync pulse pull-down enable bit (SYNC_PD)

In DSI3 mode, the SYNC_PD bit is readable and writable, but has no impact on device

operation or performance.

In SPI and I2C mode, the SYNC_PD bit is readable and writable, but has no impact on

device operation or performance.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

70 / 254

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