FXLS93421 datasheet(93/254 Pages) NXP

93 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Location

Bit

Address

$55

CH0_U_OFFSET_L

CH0_U_OFFSET[7:0]

$56

CH0_U_OFFSET_H

CH0_U_OFFSET[15:8]

$5D

CH1_U_OFFSET_L

CH1_U_OFFSET[7:0]

$5E

CH1_U_OFFSET_H

CH1_U_OFFSET[15:8]

Unprogrammed OTP Value

Table 167. User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)

The value programmed into the user offset calibration register is directly added to the

sensor data after the user sensitivity scaling but before the offset cancellation. See

Section 11.6.4.9 for scaling of the CHx_U_OFFSET value. The CHx-_U_OFFSET

LSB change in the CHx-_U_OFFSET register will result in a 1 LSB change to the value in

the SNSDATAx registers.

Note: The user offset calibration register range is larger than the full scale range of the

output. The user must take care to ensure that the value stored in this register does not

result in a compressed output range or a railed output.

11.2.32 Channel-specific status register (CH0_STAT, CH1_STAT)

The channel-specific status registers are read-only registers which contain sensor data-

specific status information.

These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming

mode.

Location

Bit

Address

$60

CH0_STAT

SIGNALCLIP

OCPHASE[2:0]

ST_INCMPLT

ST_ACTIVE

OFFSET_ERR

ST_ERROR

$70

CH1_STAT

SIGNALCLIP

OCPHASE[2:0]

ST_INCMPLT

ST_ACTIVE

OFFSET_ERR

ST_ERROR

Reset Value

Table 168. Channel-specific status register (CH0_STAT, CH1_STAT)

11.2.32.1 Signal clipped status bit (SIGNALCLIP)

In DSI3 mode, SPI mode, and I2C mode, the signal clipped status bit is set if the output

of the sinc filter reaches either the maximum or minimum value. The SIGNALCLIP bit is

cleared on a read of the CHx_STAT register through any communication interface or on a

data transmission that includes the error in the status field.

In PSI5 mode, the SIGNALCLIP bit has no impact on device operation or performance.

11.2.32.2 Offset cancellation phase status (OCPHASE[2:0])

The offset cancellation phase status bits indicate the current phase of the offset

cancellation filter as described in Section 11.6.4.6.

OCPHA

SE[2:0]

Offset cancellation startup phase

Offset low-pass filter frequency

(Hz)

000

Phase 0

163.8

001

Phase 1

40.96

010

Phase 2

10.24

Table 169. Offset cancellation phase status (OCPHASE[2:0])

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

93 / 254

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