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FXLS93421 bảng dữ liệu(PDF) 83 Page - NXP Semiconductors

tên linh kiện FXLS93421
Giải thích chi tiết về linh kiện  Dual channel inertial sensor
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FXLS93421 bảng dữ liệu(HTML) 83 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
User sensitivity
shift factor
User multiplier value
Device
type
Desired
range
(g)
Desired
sensitivity
(12 bit,
LSB/g)
NXP trim
(12 bit,
LSB/g)
U_SNS_
SHIFT (HEX)
Shift
Factor
U_SNS_-
MULT (HEX)
Multiplier
value
(Dec)
Actual
sensitivity
16 bit register
Chx_SNS-
DATAx LSB/g)
Actual
sensitivity
10 bit Sensor
data request,
LSB/g
Actual
sensitivity
12 bit Sensor
data request,
LSB/g
Actual
sensitivity
16 bit Sensor
data request,
LSB/g
500
4.0940
10.9465
0x0
0.25
0x7F
127
8.1884
1.0236
4.0942
65.5072
Note:
Table 141 includes some typical device ranges. Other ranges are possible with the user-selected shift and multiplier values.
Table 141. Example user shift and multiplier configuration for typical scale range...continued
Table 142 shows some example user shift and multiplier values for typical PSI5 full scale
ranges (± 480, 10 bit):
User sensitivity shift factor
User multiplier value
Device
type
Desired
range
(g)
Desired
sensitivity (10
bit, LSB/g)
NXP trim
(10 bit, LSB/g)
NXP trim
(16 bit, LSB/g)
U_SNS_
SHIFT (HEX)
Shift Factor
U_SNS_
MULT (HEX)
Multiplier
value
(Dec)
Actual
sensitivity
(PSI5 10
bit, LSB/g)
Actual
sensitivity
(PSI5 16
bit, LSB/g)
15
32.0000
8.2540
528.256
0x3
2
0xF0
240
31.9844
2047.00
20
24.0000
8.2540
528.256
0x3
2
0x74
116
23.9883
1535.25
30
16.0000
8.2540
528.256
0x2
1
0xF0
240
15.9922
1023.50
60
8.0000
8.2540
528.256
0x1
0.5
0xF0
240
7.9961
511.500
Medium g
120
4.0000
8.2540
528.256
0x0
0.25
0xF0
240
3.9980
255.875
60
8.0000
2.7366
175.142
0x3
2
0x76
118
7.9961
511.749
120
4.0000
2.7366
175.142
0x2
1
0x76
118
3.9980
255.874
240
2.0000
2.7366
175.142
0x1
0.5
0x76
118
1.9990
127.937
High g
480
1.0000
2.7366
175.142
0x0
0.25
0x76
118
0.9995
63.9686
Note:
Table 142 includes some typical device ranges. Other ranges are possible with the user-selected shift and multiplier values.
Table 142. Example user shift and multiplier configuration for typical psi5 scale range
11.2.25 Channel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3,
CH1_CFG_U3)
The Channel 0 and Channel 1 user configuration #3 registers are user programmable
read/write registers which contain channel-specific configuration information. The
registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$42
CH0_CFG_U3
UNSIGN
EDDATA
DATATYPE0[1:0]
DATATYPE1[2:0]
MOVEAVG[1:0]
$4A
CH1_CFG_U3
UNSIGN
EDDATA
DATATYPE0[1:0]
DATATYPE1[2:0]
MOVEAVG[1:0]
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
Table 143. Channel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3, CH1_CFG_U3)
11.2.25.1 Unsigned data select bit (UNSIGNEDDATA)
The unsigned data selection bit selects signed or unsigned data for the register and
sensor data transmissions as shown in Table 144.
Register values
DATATYPE transmissions
UNSIGN
EDDATA
CHx_SNSDATA0
CHx_SNSDATA1
Sensor data (DSI, SPI)
Sensor data (PSI5)
Channel Sensor Data
Table 144. Unsigned data select bit (UNSIGNEDDATA)
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
83 / 254



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