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FXLS93421 bảng dữ liệu(PDF) 96 Page - NXP Semiconductors

tên linh kiện FXLS93421
Giải thích chi tiết về linh kiện  Dual channel inertial sensor
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FXLS93421 bảng dữ liệu(HTML) 96 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$64
CH0_SNSDATA1_L
CH0_SNSDATA1[7:0]
$65
CH0_SNSDATA1_H
CH0_SNSDATA1[15:8]
$74
CH1_SNSDATA1_L
CH1_SNSDATA1[7:0]
$75
CH1_SNSDATA1_H
CH1_SNSDATA1[15:8]
Reset Value
0
0
0
0
0
0
0
0
Table 174. Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)
11.2.36 Channel-specific factory configuration register (CHx_CFG_F)
The channel-specific configuration registers are factory programmable OTP registers
which contain channel specific configuration information. These registers are included in
the factory programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for this register.
Location
Bit
Address Register
7
6
5
4
3
2
1
0
$A0
CH0_
CFG_F
DEV_RANGE[3:0]
RESE
RVED
RESE
RVED
AXIS[1:0]
$B0
CH1_
CFG_F
DEV_RANGE[3:0]
RESE
RVED
RESE
RVED
AXIS[1:0]
Table 175. Channel-specific factory configuration register (CHx_CFG_F)
11.2.36.1 Range indication bits (RANGE[3:0])
The range indication bits indicate the full scale range of the channel as shown in
Table 176.
RANGE[3]
RANGE[2]
RANGE[1]
RANGE[0]
Acceleration range
0
0
0
0
RESERVED
0
0
0
1
RESERVED
0
0
1
0
Medium
0
0
1
1
RESERVED
0
1
0
0
High
0
1
0
1
RESERVED
0
1
1
0
RESERVED
0
1
1
1
RESERVED
1
0
0
0
RESERVED
1
0
0
1
RESERVED
1
0
1
0
RESERVED
1
0
1
1
RESERVED
1
1
0
0
RESERVED
Table 176. Range indication bits (RANGE[3:0])
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
96 / 254



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