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FXLS93421 bảng dữ liệu(PDF) 67 Page - NXP Semiconductors |
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FXLS93421 bảng dữ liệu(HTML) 67 Page - NXP Semiconductors |
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67 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor SS_EN Data latency 0 Synchronous Sampling Mode (Latency relative to Time Slot) 1 Simultaneous Sampling Mode (Latency relative to sync pulse) Table 104. PSI5 simultaneous sampling enable (SS_EN) In SPI mode, the simultaneous sampling enable bit selects between one of two data latency methods. SS_EN Data latency 0 Synchronous sampling mode: The data for all sources is latent relative to the falling edge of slave select for the response to the Sensor Data Request for the corresponding SOURCEID. 1 Simultaneous sampling mode: The data for all sources is latent relative to the falling edge of slave select for the response to the Sensor Data Request for SOURCEID_0. If SOURCEID_0 is disabled, then the data for all SOURCEIDs is latent relative to the falling edge of slave select for the response to the Sensor Data Request for lowest enabled SOURCEID register address. Note: If multiple SOURCEIDs are enabled, sensor data for the higher SOURCEID register addresses only changes on a sensor data request for the lowest enabled SOURCEID register address. If continuous sensor data requests occur without sensor data requests for the lowest SOURCEID register address, sensor data will not be updated. Care must be taken by the user to ensure proper data transmissions. Table 105. SPI simultaneous sampling enable (SS_EN) In I2C mode, the simultaneous sampling enable bit is readable and writable but has no impact on device operation or performance. 11.2.15.4 Chip time (CHIPTIME) In DSI3 mode, the CHIPTIME bits set the chip time for Periodic Data Collection Mode as described in Table 106. The chip time for Command and Response Mode and Background Diagnostic Mode is always set to 5 µs with slew control enabled. In PSI5 mode, the CHIPTIME bits set the bit time for the PSI5 response data as described in Table 106. PSI5 DSI3 CHIPTIME[3] CHIPTIME[2] CHIPTIME[1] CHIPTIME[0] Period time Baud rate Slew control Chip time Chip rate Slew control 0 0 0 0 5.3 µs 189 kHz Enabled 1.0 µs 1000 kHz Disabled 0 0 0 1 5.3 µs 189 kHz Enabled 2.0 µs 500.0 kHz Disabled 0 0 1 0 5.3 µs 189 kHz Enabled 2.5 µs 400.0 kHz Enabled 0 0 1 1 5.3 µs 189 kHz Enabled 2.6 µs 384.6 kHz Enabled 0 1 0 0 5.3 µs 189 kHz Enabled 2.6 µs 384.6 kHz Enabled 0 1 0 1 5.3 µs 189 kHz Enabled 2.7 µs 370.3 kHz Enabled 0 1 1 0 5.3 µs 189 kHz Enabled 2.8 µs 357.1 kHz Enabled 0 1 1 1 5.3 µs 189 kHz Enabled 2.9 µs 344.8 kHz Enabled 1 0 0 0 8.0 µs 125 kHz Enabled 3.0 µs 333.3 kHz Enabled 1 0 0 1 8.0 µs 125 kHz Enabled 3.1 µs 322.6 kHz Enabled 1 0 1 0 8.0 µs 125 kHz Enabled 3.2 µs 312.5 kHz Enabled 1 0 1 1 8.0 µs 125 kHz Enabled 3.3 µs 303.0 kHz Enabled 1 1 0 0 8.0 µs 125 kHz Enabled 3.5 µs 294.1 kHz Enabled Table 106. Chip time (CHIPTIME) FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 67 / 254 |
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