FXLS93421 datasheet(60/254 Pages) NXP

60 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Notes:

• In PSI5 / SPI mode (COMMTYPE = 1), SPI transactions are ignored by the device until

PSI5 initialization 3 is complete. SPI Test Mode Entry is not restricted.

• In PSI5 / SPI mode (COMMTYPE = 1), only SPI read register transactions are

available.

• In DSI3 / SPI mode (COMMTYPE = 0) and PSI5 / SPI mode (COMMTYPE = 1),

registers accesses by protocol are completed in the order received. Care must be

taken to prevent from incorrect addressing of the F, UF0, and UF1 registers.

• In SPI only mode and in I2C only mode, the BUS_I undervoltage detection is disabled

to allow for 3.3 V system operation. the VBUF undervoltage detection replaces the

BUS_I undervoltage detection.

• If the COMMTYPE register is pre-programmed in OTP to a specific communication

type, the user must prevent writes to this register when writing the UF2 register to OTP.

If a pre-programmed COMMTYPE register is over-written and then written to OTP, the

UF2 CRC verification will fail.

11.2.12 Physical address register (PHYSADDR)

The physical address register is a user programmed OTP register which contains the

physical address of the slave for use in DSI3. This register is included in the read/write

array error detection. If the physical address stored in the OTP array is zero, the address

is assigned either during Discovery Mode or during Command and Response Mode.

If the physical address stored in the OTP array is non-zero, the device ignores Discovery

Mode and uses the programmed physical address for Command and Response Mode.

The physical address register value can be changed by a Command and Response

Mode register write command. However, if the UF2 region is locked, the value will always

be reset to the OTP array value after a reset.

In SPI mode, I2C mode and PSI5 mode, the PHYSADDR register is readable and

writable, but has no impact on device operation or performance.

Location

Bit

Address

$18

PHYS

ADDR

PADDR[3:0]

Unprogrammed

OTP Value

Table 88. Physical address register (PHYSADDR)

11.2.13 Source identification registers (SOURCEID_x)

The source identification registers are user programmed read/write registers which

contain the source identification information used for DSI3 PDCM, PSI5 mode, and SPI

Mode. These registers are included in the read/write array error detection.

These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$1A

SOURCEID_0

SID0_EN

PDCMFORMAT[2:0]

SOURCEID_0[3:0]

Table 89. Source identification registers (SOURCEID_x)

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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