FXLS93421 datasheet(148/254 Pages) NXP

148 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

12.1 DSI3 physical layer

12.1.1 Command receiver

The command receive block converts voltage transitions on the BUS_I pin to a digital

pulse train for decoding by the DSI data link layer.

The supply voltage can vary throughout the specified range, so the communication high

voltage (VHIGH) must be sampled and averaged with a low-pass filter. The communication

low voltage is then determined by comparing the supply voltage to the sampled and

averaged VHIGH voltage. Figure 62 shows a block diagram of the command receiver

physical layer.

aaa-030645

2.8 MΩ

2.2 MΩ

lpf_reset

11 R

54 pF

DSI3

DSI3/PSI5

41.66 mV 83.33 mV

bus in

Vbufa

command_detect

fOSC

count

command_detect

COUNTER

command

cmd_block

cmd_start

cmd_valid

Vhigh_sample

CONTROL

LOGIC

DSI/PSI

Figure 62. Command receiver physical layer

The start of a command is detected when the comparator output (Command_Detect) is

low. The comparator output is input to a counter that is updated at the internal oscillator

frequency. Control logic monitors the counter output and generates the necessary

internal signals for the logic.

Figure 63 shows a timing diagram of the command receiver when a valid command is

received, and Figure 64 shows a timing diagram of the command receiver when a micro-

cut is received during the command window. Voltage values and timing parameters are

specified in Section 10.4 and Section 10.20.

aaa-030646

time

BUS_I

Cmd_Start

tCmd_Valid

tCmdBlock_ST_CRM

Cmd_Valid

Cmd_Block

VHigh_Samp

tCmdBlock_CRM

Figure 63. DSI3 command receiver timing diagram: valid command

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

148 / 254

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