HCS08 datasheet(305/374 Pages) NXP

305 / 374 page

Universal Serial Bus Device Controller (S08USBV1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

305

17.3.9

Status Register (STAT)

The STAT reports the transaction status within the USB module. When the MCU receives a TOKDNE

interrupt, the STAT is read to determine the status of the previous endpoint communication. The data in

the status register is valid only when the TOKDNEF interrupt flag is asserted. The STAT register is actually

a read window into a status FIFO maintained by the USB module. When the USB module uses a BD, it

updates the status register. If another USB transaction is performed before the TOKDNE interrupt is

serviced, the USB module will store the status of the next transaction in the STAT FIFO. Thus, the STAT

serial interface engine (SIE) is processing the next. Clearing the TOKDNEF bit in the INTSTAT register

causes the SIE to update the STAT register with the contents of the next STAT value. If the next data in the

STAT FIFO holding register is valid, the SIE will immediately reassert the TOKDNE interrupt.

CRC5

CRC5 Interrupt Enable — Setting this bit will enable CRC5 interrupts.

0 Interrupt disabled

1 Interrupt enabled

PIDERR

PIDERR Interrupt Enable — Setting this bit will enable PIDERR interrupts.

0 Interrupt disabled

1 Interrupt enabled

321

ENDP[3:0]

ODD

Reset

000

= Unimplemented or Reserved

Figure 17-12. Status Register (STAT)

Table 17-13. STAT Field Descriptions

Field

Description

7–4

ENDP[3:0]

Endpoint Number — These four bits encode the endpoint address that received or transmitted the previous

token. This allows the microcontroller to determine which BDT entry was updated by the last USB transaction.

0000 Endpoint 0

0001 Endpoint 1

0010 Endpoint 2

0011 Endpoint 3

0100 Endpoint 4

0101 Endpoint 5

0110 Endpoint 6

Table 17-12. ERRSTAT Field Descriptions (continued)

Field

Description

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