HCS08 datasheet(84/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin

control registers. This section refers to registers and control bits only by their names. A Freescale-provided

equate or header file normally is used to translate these names into the appropriate absolute addresses.

6.5.1

Port A I/O Registers (PTAD and PTADD)

Port A parallel I/O function is controlled by the registers listed below.

6.5.2

Port A Pin Control Registers (PTAPE, PTASE, PTADS)

In addition to the I/O control, port A pins are controlled by the registers listed below.

321

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

Reset

000

Figure 6-2. Port A Data Register (PTAD)

Table 6-1. PTAD Register Field Descriptions

Field

Description

5:0

PTAD[5:0]

Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pullups disabled.

321

PTADD5

PTADD4

PTADD3

PTADD2

PTADD1

PTADD0

Reset

000

Figure 6-3. Data Direction for Port A Register (PTADD)

Table 6-2. PTADD Register Field Descriptions

Field

Description

5:0

PTADD[5:0]

Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for

PTAD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

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