HCS08 datasheet(75/374 Pages) NXP

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Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

must be written during the user’s reset initialization program to set the desired controls even if the desired

settings are the same as the reset settings.

321

COPT

STOPE

Reset

110

011

= Unimplemented or Reserved

Figure 5-5. System Options Register (SOPT1)

Table 5-5. SOPT1 Register Field Descriptions

Field

Description

7:6

COPT[1:0]

COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with

COPCLKS in SOPT2 defines the COP timeout period. See Table 5-6.

STOPE

Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is

disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.

0 Stop mode disabled.

1 Stop mode enabled.

Table 5-6. COP Configuration Options

Control Bits

Clock Source

COP Window1 Opens

(COPW = 1)

1 Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column

displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode

(COPW = 1).

COP Overflow Count

COPCLKS

COPT[1:0]

N/A

0:0

N/A

COP is disabled

0:1

1 kHz LPO

clock

N/A

25 cycles (32 ms2)

2 Values shown in milliseconds based on t

LPO = 1 ms. See tLPO in the appendix Section A.12.1, “Control Timing,” for the

tolerance of this value.

1:0

1 kHz LPO

clock

N/A

28 cycles (256 ms1)

1:1

1 kHz LPO

clock

N/A

210 cycles (1.024 s1)

10:1

BUSCLK

6144 cycles

213 cycles

11:0

BUSCLK

49,152 cycles

216 cycles

11:1

BUSCLK

196,608 cycles

218 cycles

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