HCS08 datasheet(90/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

6.5.7

Port D I/O Registers (PTDD and PTDDD)

Port D parallel I/O function is controlled by the registers listed below.

6.5.8

Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)

In addition to the I/O control, port D pins are controlled by the registers listed below.

321

PTDD7

PTDD6

PTDD5

PTDD4

PTDD3

PTDD2

PTDD1

PTDD0

Reset

000

Figure 6-17. Port D Data Register (PTDD)

Table 6-16. PTDD Register Field Descriptions

Field

Description

7:0

PTDD[7:0]

Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pullups disabled.

321

PTDDD7

PTDDD6

PTDDD5

PTDDD4

PTDDD3

PTDDD2

PTDDD1

PTDDD0

Reset

000

Figure 6-18. Data Direction for Port D (PTDDD)

Table 6-17. PTDDD Register Field Descriptions

Field

Description

7:0

PTDDD[7:0]

Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for

PTDD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.

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