HCS08 datasheet(71/374 Pages) NXP

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Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

5.6

Low-Voltage Detect (LVD) System

The MC9S08JM60 series includes a system to protect against low-voltage conditions in order to protect

memory contents and control MCU system states during supply voltage variations. The system is

comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and

detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon

entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then

the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the

LVD enabled will be higher.

5.6.1

Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset

rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the

LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low

threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2

Low-Voltage Detection (LVD) Reset Operation

The LVD can be configured to generate a reset upon detection of a low voltage condition by setting

LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has

occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low

voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.

5.6.3

Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is

approaching the low voltage condition. When a low voltage warning condition is detected and is

configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt

request will occur.

0xFFFC:FFFD

Vswi

Core

SWI Instruction

—

Software interrupt

0xFFFE:FFFF

Vreset

System

control

COP

LVD

RESET pin

Illegal opcode

LOC

POR

BDFR

COPE

LVDRE

—

ILOP

CME

POR

BDFR

Watchdog timer

Low-voltage detect

External pin

Illegal opcode

Loss of clock

Power-on-reset

BDM-forced reset

Table 5-1. Vector Summary (from Lowest to Highest Priority) (continued)

Vector

Number

Address

(High/Low)

Vector Name

Module

Source

Enable

Description

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