HCS08 datasheet(96/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

6.5.13

Port G I/O Registers (PTGD and PTGDD)

Port G parallel I/O function is controlled by the registers listed below.

6.5.14

Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)

In addition to the I/O control, port G pins are controlled by the registers listed below.

321

PTGD5

PTGD4

PTGD3

PTGD2

PTGD1

PTGD0

Reset

000

Figure 6-32. Port G Data Register (PTGD)

Table 6-31. PTGD Register Field Descriptions

Field

Description

5:0

PTGD[5:0]

Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also

configures all port pins as high-impedance inputs with pullups disabled.

321

PTGDD5

PTGDD4

PTGDD3

PTGDD2

PTGDD1

PTGDD0

Reset

000

Figure 6-33. Data Direction for Port G (PTGDD)

Table 6-32. PTGDD Register Field Descriptions

Field

Description

5:0

PTGDD[5:0]

Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for

PTGD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.

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