HCS08 datasheet(22/374 Pages) NXP

22 / 374 page

Chapter 1 Device Overview

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

Figure 1-2. System Clock Distribution Diagram

The MCG supplies the following clock sources:

•

MCGOUT — This clock source is used as the CPU, USB RAM and USB module clock, and is

divided by two to generate the peripheral bus clock (BUSCLK). Control bits in the MCG control

registers determine which of the three clock sources is connected:

— Internal reference clock

— External reference clock

— Frequency-locked loop (FLL) or Phase-locked loop (PLL) output

See Chapter 12, “Multi-Purpose Clock Generator (S08MCGV1),” for details on configuring the

MCGOUT clock.

•

MCGLCLK — This clock source is derived from the digitally controlled oscillator (DCO) of the

MCG. Development tools can select this internal self-clocked source to speed up BDC

communications in systems where the bus clock is slow.

•

MCGIRCLK — This is the internal reference clock and can be selected as the real-time counter

clock source. Chapter 12, “Multi-Purpose Clock Generator (S08MCGV1),” explains the

MCGIRCLK in more detail. See Chapter 13, “Real-Time Counter (S08RTCV1),” for more

information regarding the use of MCGIRCLK.

•

MCGERCLK — This is the external reference clock and can be selected as the clock source of

real-time counter and ADC module. Section 12.4.6, “External Reference Clock,” explains the

MCGERCLK in more detail. See Chapter 13, “Real-Time Counter (S08RTCV1),” and Chapter 10,

TPM1

TPM2

IIC

SCI1

SCI2

BDC

CPU

ADC2

RAM

Flash3

MCG

MCGOUT

÷2

BUSCLK

MCGLCLK

MCGERCLK

COP

1. The FFCLK is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency.

3. Flash has the frequency requirements for program and erase operation. See the Appendix A, “Electrical Characteristics,” for

details.

2. ADC has min. and max. frequency requirements. See Chapter 10, “Analog-to-Digital Converter (S08ADC12V1),”

and Appendix A, “Electrical Characteristics,” for details.

XOSC

EXTAL

XTAL

SPI1

FFCLK1

MCGFFCLK

RTC

1 kHz

LPO

TPMCLK

MCGIRCLK

÷2

SPI2

USB

USB RAM

LPO clock

HCS08 bảng dữ liệu(PDF) 22 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL